parttime Asic-ontwerper vacatures

Lead Hardware Security Engineer

Other Engineering

Posted on Dec 2, 2025

Lead Hardware Security Engineer

Job Locations NL-Rotterdam

Job ID 2025-22441EV

Category Engineering

Overview

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional ASIC Security Engineer to join our Security IP team in the Netherlands (Vught or Rotterdam, NL). Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

As an ASIC Security Engineer, you'll play a pivotal role in architecting and developing security IPs including Random Number Generators and various Crypto Cores, and contribute to the Root-of-Trust products. In this full-time role, you'll report directly to our Security Engineering Manager. Silicon IP team is dedicated to design with Rambus's quality standard and awareness of safety and security while maintaining the high configurability of the product.

Rambus offers a flexible work environment , embracing a hybrid approach for most office-based roles . E mployees are encouraged to spend an average of at least three days per week onsite , allowing for two days of remote work .

Responsibilities

• Develop, analyze and model novel random number generators
• Research, invent and patent/publish new techniques in the field of security
• Work closely with the architects to contribute to the design of various crypto cores and the Crypto-Manager Root-of-Trust product.
• Cooperate with the Software Team, Product Managers, Security experts and other stakeholders to support the current and next generation security products and their certification effort.
• Drive design improvements for continuous product quality and safety.
• Assure the delivered product and documentation adheres to Rambus quality and safety standards.

Qualifications

• Experience/Skills
  • MS/PhD degree in electrical or computer engineering required.
  • 4 plus years working in random number generators and secure hardware design, a PhD degree may substitute the work experience requirement
  • Demonstrated proficiency in Verilog/(or VHDL) and digital design.
  • Familiarity with front-end ASIC design flows, including design, synthesis, timing analysis, logical equivalence checking, and linting/rule checking
  • Expertise in some or all of the following areas is beneficial:
    • Cryptographic algorithms and side-channel attacks
    • Experience with back-end flows, especially place-and-route
    • DFT, especially testing and characterization and/or Logic BIST methodologies.
    • Hardware development experience in UNIX/Linux environments, including supporting tasks such as shell scripting and basic Perl scripts.
• Tools/Technologies
  • Verilog (or VHDL), SystemVerilog, Perl
  • Shell scripting, Python, Tcl
  • Xilinx Vivado,
  • Unix, Linux
  • Front-end ASIC design tools, such as
    • Synopsys Design Compiler
    • Cadence Genus
    • Synopsys Spyglass
    • Cadence Conformal(-LP)
  • ASIC simulation/verification tools, such as
    • Cadence Xcelium
    • Synopsys Verdi
      • Mentor Questa Formal Verification

About Rambus

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow's systems.

Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.

At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures.